1. Field of the Invention
This invention relates to a device evaluation circuit used to evaluate electric characteristics of a semiconductor device (hereinafter called "IC") or the like of a type wherein elements such as a GaAs (Gallium Arsenide) field effect transistor, etc. are incorporated in a package, and capable of matching the impedance of a measurement system to that of the IC.
2. Description of the Related Art
FIG. 2 is a perspective view showing an essential part of a conventional device evaluation circuit.
The device evaluation circuit is used to evaluate dc and high-frequency electric characteristics of an IC. The device evaluation circuit comprises a board or substrate 10 and a ceramic head 20 which serves as an evaluation jig. A co-planar distributed constant circuit made up of a micro strip line 11 used as a central conductor and ground conductors 12 placed on both sides of the micro strip line 11 at a predetermined distance away is formed on the surface of the substrate 10. Each of the ground conductors 12 is electrically connected to a ground placed on the lower side of the substrate 10 through an unillustrated through hole or the like. An accommodation or storage part 13 opened by cutting the micro strip line 11 is formed in the center of the substrate 10. The ceramic head 20 is held in the storage part 13 so as to be insertable therein and removable therefrom. The ceramic head 20 comprises a pedestal or base 21 made of a conductive metal, ceramic plates 22 and 23 used as insulative members, which are fixed onto the base 21 with a predetermined interval defined therebetween, and micro strip lines 24 and 25 used as wiring patterns, which are respectively formed on the ceramic plates 22 and 23. The base 21 is electrically connected to the ground by being held within the storage part 13. The micro strip lines 24 and 25 are electrically connected to the cut micro strip lines 11 placed on both sides of the substrate 10.
An IC 30 is mounted between the ceramic plates 22 and 23 of the ceramic head 20. The IC 30 has a GaAs FET incorporated therein. A gate terminal 31 of the FET incorporated in the IC 30 is electrically connected to the micro strip line 24. Further, a drain terminal 32 thereof is electrically connected to the micro strip line 25 and a source terminal 33 thereof is electrically connected to the base 21.
When the entire device evaluation circuit is made up of a lexolight substrate or the like, the ceramic head 20 presents a problem in durability when it is desired to evaluate many ICs 30 or the like. Therefore, the ceramic head 20 is held within the substrate 10 to ensure the durability.
Upon evaluating a high-frequency characteristic of the IC 30, it is necessary to match the characteristic impedance of the IC 30 to that of an unillustrated external measurement system for inputting a signal to and outputting it from the IC 30 through the micro strip lines 11, 24 and 25. When the characteristic impedances are mismatched to each other, power is reflected from a junction point and hence the original characteristic of the IC 30 cannot be evaluated. The device evaluation circuit serves as a characteristic impedance converter for making a match between the characteristic impedance of the measurement system and that of the IC 30 (for matching the characteristic impedance of the measurement system to that of the IC 30). Matching elements or devices 35 such as trimmer condensers whose capacitance values are variable, chip capacitors or chip coils or the like, are mounted between the cut micro strip lines 11 and each of the ground conductors 12. The matching devices 35 are mounted therebetween and the matching of the characteristic impedances between the measurement system and the IC 30 is done, whereby the characteristic of the IC 30 is evaluated.
However, the conventional device evaluation circuit has the following problems:
A characteristic impedance of a general measurement system is 50 ohms and a characteristic impedance of an IC 30 available for power application is about a few ohms. The more the difference between the characteristic impedances increases, the more difficult the fabrication of a matching circuit becomes. As the characteristic impedance of the IC 30 becomes small in particular, it becomes hard to match the characteristic impedance of the IC 30 to that of the measurement system. On the other hand, since the gate width is increased to provide a large current flow in the recently-available IC 30, input/output characteristic impedances are significantly reduced. Since the characteristic impedance of the micro strip line 11 is 50 ohms and the characteristic impedances of the micro strip lines 24 and 25 of the ceramic head 20 are respectively about 20 ohms, for example, the implementation of the matching devices 35 becomes effected at their corresponding positions near the IC 30 to form a matching circuit for the IC 30 having such low input/output characteristic impedances. In the device evaluation circuit using the insertable and removable ceramic head 20 or the like, however, the matching devices 35 such as the capacitors or the like cannot be implemented in the vicinity of the IC 30.
There may be cases in which the gate terminal 31 and drain terminal 32 of the IC 30 are respectively biased to suitable potentials upon measuring and evaluating the electric characteristic. The placement of bias lines for providing such biasing in the vicinity of the IC 30 allows a reduction in loss developed upon measurement of the electric characteristic. However, the device evaluation circuit using the ceramic head 20 or the like shown in FIG. 2 has a problem in that the bias lines are placed on the substrate 10 side and their positions to apply the bias to the IC 30 are distant.